The present invention is directed, in general, to test apparatus and, more specifically, to an automated system for estimating ring oscillator (RO) reliability and testing AC circuit response and method of operating the same to test a sample of ROs and determine overall reliability based thereon.
In the production of integrated circuits (ICs), considerable testing must be done to determine the IC parameters and whether the IC performs its intended function. In this regard, comprehensive testing regimens have been developed. The particular procedure used to carry out a test depends, of course, upon the type of IC being tested and the individual parameters of concern in a particular application. Nonetheless, tests commonly performed on ICs include determining circuit aging and alternating current (AC) testing of individual IC devices.
The procedures for determining circuit aging and for performing AC testing are well known in the art. Typically, analysis of a frequency of a ring oscillator associated with the IC is used to determine circuit aging. More specifically, a stress voltage, in addition to an operating voltage, is applied through the ring oscillator and across an IC device under test so that degradation in the ring oscillator frequency can be determined. Such degradation is measured and determined with a circuit analyzing device, such as an oscilloscope. Performing circuit aging testing by way of determining degradation in ring oscillator frequency is described in greater detail in Intl. Electron Device Meeting (IEDM), 1998, Short Course, San Francisco, Calif., Peng Fang, et al., which is incorporated herein by reference in its entirety.
For AC testing, operating and stress voltages are applied across the device under test so that the circuit analyzing device can be used to measure and determine the operating speed of that particular IC. Performing AC testing for determining operating speed of an IC is described in greater detail in Intl. Conf. on Microelectronic Test Structures (ICMTS), 2000, Monterey, Calif., S. Chetlur, et al., which is also incorporated herein by reference in its entirety, and more particularly on page 163 thereof. Those skilled in the pertinent art understand that determining the rate at which an IC ages, as well as its operating speed, are essential when manufacturing a product having IC devices included therein.
Performing these tests on semiconductor devices, such as ICs, at the singulated device level, i.e. prior to permanent mounting on an interconnection substrate, is typically conducted with an apparatus constructed on the xe2x80x9cbed of nailsxe2x80x9d principle. Under this principle, the devices under test are usually ball-grid array or solder-bumped ICs with perimeter arrays or area arrays of contacts on one side of the device. The array of contacts is used, after successful test, to, for example, xe2x80x9cflip-chipxe2x80x9d bond the device to an interconnection substrate.
The apparatus for conducting these tests typically has a large x-y array of contact pins that are brought into contact with the predetermined portions of the device under test. Specifically, the pins in the x-y array of the test apparatus that align with the pads or bumps on the device are addressed with appropriate electrical circuitry in the test apparatus to apply test voltages (operating and stress voltages) to the device contacts and measure the electrical characteristics of the device with a circuit analyzer. Some testers are universal in the sense that pins in the x-y test array contact any given contact pattern so that different devices with different contact patterns can be tested by modifying the software used to address the array of test pins. However, testers can also be made with a permanent custom pin array tailored to a particular IC device design.
Although the mechanical constructs of testers used to determine IC aging and operating speed allows such testers to perform accurately, procedural aspects associated with performing such tests remain costly and time-consuming. For example, in conventional test procedures found in the prior art, intervention by a human operator is still required to gather the information needed to determine circuit aging and operating speed of the devices under test. Specifically, prior art testing systems require an operator to manually measure the degradation in ring oscillator frequency, as well as perform the AC testing, after a stress cycle of the device under test is completed. In addition, the operator is also required to begin the next stress cycle, and then return to take measurements again after the next stress cycle is complete.
Unfortunately, numerous disadvantages exist when operator intervention is required. First, the costs associated with staffing experienced operators in a testing facility can be quite large. Second, in some cases a stress cycle may end at an odd time, perhaps late in the evening, requiring the operator to be present at an unusual hour. Third, even beyond the need to work late hours, the accuracy of an operator""s measurements at such late hours may also come into question. Finally, conventional tests for determining circuit aging and operating speed of IC devices usually last for two to three months at a time. Thus, devoting the resources of an operator over such a prolonged period of time may not be cost-effective when that operator""s time may be better suited for other tasks.
Accordingly, what is needed in the art is a system for determining circuit aging of IC devices, as well as determining the operating speed of those devices, that does not suffer from the disadvantages found in prior art systems.
To address the above-discussed deficiencies of the prior art, the present invention provides an automated system for, and method of, estimating ring oscillator reliability and testing AC response of a device under test (DUT). In one embodiment, the system includes: (1) a DUT board that accepts, and allows electrical communication with, a plurality of DUTs, (2) a power source, couplable to the DUT board, that provides AC power of controllable characteristics to the plurality of DUTs and (3) an automated switching matrix, couplable between the DUT board and a circuit analyzer, that allows the circuit analyzer to analyze ring oscillators and predetermined portions of the plurality of DUTs at predetermined times as the power source provides the power thereto.
The present invention automates and significantly enhances the integrity of ring oscillator aging and AC response tests for devices such as those embodied in ICs.
In one embodiment of the present invention, the DUT board accepts eight of the DUTs. Of course, other numbers of DUTs per DUT board are within the broad scope of the present invention.
In one embodiment of the present invention, the automated switching matrix is a first automated switching matrix and the system further comprises a second automated switching matrix interposed between the first automated switching matrix and the circuit analyzer, the first and second automated switching matrices cooperating to allow the circuit analyzer to analyze the ring oscillators and the predetermined portions.
In one embodiment of the present invention, the circuit analyzer is an oscilloscope. Other circuit analyzers are, however, within the broad scope of the present invention.
In one embodiment of the present invention, the system further includes a chassis having a backplane bus that intercouples the DUT board, the switching matrix and the circuit analyzer. In a more specific embodiment, the system takes the form of a chassis that accepts DUT boards, switching matrices and the circuit analyzer as modules or boards therein.
In one embodiment of the present invention, the system further includes an environmental chamber for containing the DUT board and capable of subjecting the DUT board to a predetermined environment. The environmental chamber allows temperature and humidity, as well as any other desired physical, environmental attribute to be varied as desired to further testing.
In one embodiment of the present invention, the system further includes a network interface that allows the circuit analyzer to communicate via a computer network. The network interface, while not necessary to the present invention, advantageously allows testing to be initiated, terminated and monitored remotely.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the pertinent art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the pertinent art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the pertinent art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.